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No FPU in fx-9860G II?

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Posts: 13
Joined: Wed Sep 21, 2016 7:41 pm
Calculators: Casio Afx 2.0, Casio fx-9860 G SD

No FPU in fx-9860G II?

Postby toml_12953 » Sun Sep 25, 2016 9:14 am

Is it true that there's no FPU in the SH-4 used in the fx-9860G II USB Power Graphic 2 calculator?
If so, what other parts of the SH-4 manual don't apply to the customized version found in the Casio?

Tom L

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Calculators: Casio fx-7400GII, Casio fx-7400GII (SH4), Casio fx-9750 G II, Casio fx-9750 G II (SH4), Casio fx-9860G, Casio fx-9860 G SD, Casio fx-9860G Slim, Casio fx-9860 GII SD, Casio fx-9860 GII SD Power Graphic 2, Casio Classpad 330 plus, Casio fx-CG 20, Casio Classpad fx-cp400, Casio fx-CG 50

Re: No FPU in fx-9860G II?

Postby SimonLothar » Tue Sep 27, 2016 9:20 pm

A few years ago TeamFX told me, the SH7305 is a SH4AL-DSP and that according to bit 29 of the Cache Version Register (0xFF000040), it has no FPU.
In these days I made some tests and could not detect a FPU.

Here you have a complete list of all SH7305 registers. All SH7724 registers/modules, which you cannot identify in this list, are probably not supported by the SH7305.
SH7305 registers: Show
FF000020 dd dd TRA (Trap event)
FF000024 dd dd EXPEVT (Exception event)
FF2F0004 dd dd EXPMASK (Nonsupport exception event)
FF2F0000 dd dd CPUOPM (CPU operation mode)
FF000030 dd dd PVR (Processor version)
FF000040 dd dd CVR (Cache Version) (undocumented)
FF000044 dd dd PRR (Product version)

PFC (Port function control)
A4050100 dw dw PACR (Port A Control)
A4050102 dw dw PBCR (Port B Control)
A4050104 dw dw PCCR (Port C Control)
A4050106 dw dw PDCR (Port D Control)
A4050108 dw dw PECR (Port E Control)
A405010A dw dw PFCR (Port F Control)
A405010C dw dw PGCR (Port G Control)
A405010E dw dw PHCR (Port H Control)
A4050110 dw dw PJCR (Port J Control)
A4050112 dw dw PKCR (Port K Control)
A4050114 dw dw PLCR (Port L Control)
A4050116 dw dw PMCR (Port M Control)
A4050118 dw dw PNCR (Port N Control)
A405014C dw dw PPCR (Port P Control)
A405011A dw dw PQCR (Port Q Control)
A405011C dw dw PRCR (Port R Control)
A405011E dw dw PSCR (Port S Control)
A4050140 dw dw PTCR (Port T Control)
A4050142 dw dw PUCR (Port U Control)
A4050144 dw dw PVCR (Port V Control)
A405014E dw dw PSELA (Pin group A select)
A4050150 dw dw PSELB (Pin group B select)
A4050152 dw dw PSELC (Pin group C select)
A4050154 dw dw PSELD (Pin group D select)
A4050156 dw dw PSELE (Pin group E select)
A405015E dw dw PSELF (Pin group F select)
A40501C8 dw dw PSELG (Pin group G select)
A40501D6 dw dw PSELH (Pin group H select)
A4050158 dw dw HIZCRA (Data pin Hi-Z control A)
A405015A dw dw HIZCRB (Data pin Hi-Z control B)
A405015C dw dw HIZCRC (Data pin Hi-Z control C)
A4050180 dw dw MSELCRA (Module function select A)
A4050182 dw dw MSELCRB (Module function select B)
A4050186 dw dw DRVCRA (Buffer drive control A)
A4050188 dw dw DRVCRB (Buffer drive control B)
A405018A dw dw DRVCRC (Buffer drive control C)
A4050184 dw dw DRVCRD (Buffer drive control D)
A40501C3 db db PULCRBSC (BSC pull-up/down control)
A40501C5 db db PULCRTRST (TRST pull-up/down select)
A4050190 db db PULCRA (Port A pull-up/down control)
A4050191 db db PULCRB (Port B pull-up/down control)
A4050192 db db PULCRC (Port C pull-up/down control)
A4050193 db db PULCRD (Port D pull-up/down control)
A4050194 db db PULCRE (Port E pull-up/down control)
A4050195 db db PULCRF (Port F pull-up/down control)
A4050196 db db PULCRG (Port G pull-up/down control)
A4050197 db db PULCRH (Port H pull-up/down control)
A4050198 db db PULCRJ (Port J pull-up/down control)
A4050199 db db PULCRK (Port K pull-up/down control)
A405019A db db PULCRL (Port L pull-up/down control)
A405019B db db PULCRM (Port M pull-up/down control)
A405019C db db PULCRN (Port N pull-up/down control)
A40501C6 db db PULCRP (Port P pull-up/down control)
A405019D db db PULCRQ (Port Q pull-up/down control)
A405019E db db PULCRR (Port R pull-up/down control)
A405019F db db PULCRS (Port S pull-up/down control)
A40501C0 db db PULCRT (Port T pull-up/down control)
A40501C1 db db PULCRU (Port U pull-up/down control)
A40501C2 db db PULCRV (Port V pull-up/down control)

IO (Port I/O)
A4050120 db db PADR (Port A data)
A4050122 db db PBDR (Port B data)
A4050124 db db PCDR (Port C data)
A4050126 db db PDDR (Port D data)
A4050128 db db PEDR (Port E data)
A405012A db db PFDR (Port F data)
A405012C db db PGDR (Port G data)
A405012E db db PHDR (Port H data)
A4050130 db db PJDR (Port J data)
A4050132 db db PKDR (Port K data)
A4050134 db db PLDR (Port L data)
A4050136 db db PMDR (Port M data)
A4050138 db db PNDR (Port N data)
A405016A db db PPDR (Port P data)
A405013A db db PQDR (Port Q data)
A405013C db db PRDR (Port R data)
A405013E db db PSDR (Port S data)
A4050160 db db PTDR (Port T data)
A4050162 db db PUDR (Port U data)
A4050164 db db PVDR (Port V data)

INT (Interrupt)
A4080000 dw dw IPRA (Interrupt priority A)
A4080004 dw dw IPRB (Interrupt priority B)
A4080008 dw dw IPRC (Interrupt priority C)
A408000C dw dw IPRD (Interrupt priority D)
A4080010 dw dw IPRE (Interrupt priority E)
A4080014 dw dw IPRF (Interrupt priority F)
A4080018 dw dw IPRG (Interrupt priority G)
A408001C dw dw IPRH (Interrupt priority H)
A4080020 dw dw IPRI (Interrupt priority I)
A4080024 dw dw IPRJ (Interrupt priority J)
A4080028 dw dw IPRK (Interrupt priority K)
A408002C dw dw IPRL (Interrupt priority L)
A4140000 dw dw ICR0 (Interrupt control 0)
A414001C dw dw ICR1 (Interrupt control 1)
A4140010 dd dd INTPRI00 (Interrupt priority for IRQ)
A4140024 db db INTREQ00 (Interrupt request for IRQ)
A4140044 db db INTMSK00 (Interrupt mask for IRQ)
A4140064 db db INTMSKCLR00 (Interrupt mask clear for IRQ)
A41400C0 dw dw NMIFCR (Interrupt control for NMI)
A4700000 00000032 00000020 USERIMASK (User interrupt mask)
FF000028 dd dd INTEVT (Interrupt event)
A40501DC dw dw PINTCRA (PINT control A)
A40501DE dw dw PINTCRB (PINT control B)
A40501EA db db PINTSRA (PINT status A)
A40501EC db db PINTSRB (PINT status B)
A40501EE db db PINTSRC (PINT status C)
A40501FA db db PINTSRD (PINT status D)
A4080080 db db IMR0 (Interrupt mask 0)
A40800C0 db db IMCR0 (Interrupt mask clear 0)
A4080084 db db IMR1 (Interrupt mask 1)
A40800C4 db db IMCR1 (Interrupt mask clear 1)
A4080088 db db IMR2 (Interrupt mask 2)
A40800C8 db db IMCR2 (Interrupt mask clear 2)
A408008C db db IMR3 (Interrupt mask 3)
A40800CC db db IMCR3 (Interrupt mask clear 3)
A4080090 db db IMR4 (Interrupt mask 4)
A40800D0 db db IMCR4 (Interrupt mask clear 4)
A4080094 db db IMR5 (Interrupt mask 5)
A40800D4 db db IMCR5 (Interrupt mask clear 5)
A4080098 db db IMR6 (Interrupt mask 6)
A40800D8 db db IMCR6 (Interrupt mask clear 6)
A408009C db db IMR7 (Interrupt mask 7)
A40800DC db db IMCR7 (Interrupt mask clear 7)
A40800A0 db db IMR8 (Interrupt mask 8)
A40800E0 db db IMCR8 (Interrupt mask clear 8)
A40800A4 db db IMR9 (Interrupt mask 9)
A40800E4 db db IMCR9 (Interrupt mask clear 9)
A40800A8 db db IMR10 (Interrupt mask 10)
A40800E8 db db IMCR10 (Interrupt mask clear 10)
A40800AC db db IMR11 (Interrupt mask 11)
A40800EC db db IMCR11 (Interrupt mask clear 11)
A40800B0 db db IMR12 (Interrupt mask 12)
A40800F0 db db IMCR12 (Interrupt mask clear 12)

DMA (DMA Controller)
FE008020 dd dd SAR0 (DMA0 Source address)
FE008024 dd dd DAR0 (DMA0 Dest address)
FE008028 dd dd TCR0 (DMA0 Count)
FE00802C dd dd CHCR0 (DMA0 Control)
FE008030 dd dd SAR1 (DMA1 Source address)
FE008034 dd dd DAR1 (DMA1 Dest address)
FE008038 dd dd TCR1 (DMA1 Count)
FE00803C dd dd CHCR1 (DMA1 Control)
FE008040 dd dd SAR2 (DMA2 Source address)
FE008044 dd dd DAR2 (DMA2 Dest address)
FE008048 dd dd TCR2 (DMA2 Count)
FE00804C dd dd CHCR2 (DMA2 Control)
FE008050 dd dd SAR3 (DMA3 Source address)
FE008054 dd dd DAR3 (DMA3 Dest address)
FE008058 dd dd TCR3 (DMA3 Count)
FE00805C dd dd CHCR3 (DMA3 Control)
FE008060 dw dw DMAOR (DMA Operation)
FE008070 dd dd SAR4 (DMA4 Source address)
FE008074 dd dd DAR4 (DMA4 Dest address)
FE008078 dd dd TCR4 (DMA4 Count)
FE00807C dd dd CHCR4 (DMA4 Control)
FE008080 dd dd SAR5 (DMA5 Source address)
FE008084 dd dd DAR5 (DMA5 Dest address)
FE008088 dd dd TCR5 (DMA5 Count)
FE00808C dd dd CHCR5 (DMA5 Control)
FE008120 dd dd SARB0 (DMA0 Source address B)
FE008124 dd dd DARB0 (DMA0 Dest address B)
FE008128 dd dd TCRB0 (DMA0 Count B)
FE008130 dd dd SARB1 (DMA1 Source address B)
FE008134 dd dd DARB1 (DMA1 Dest address B)
FE008138 dd dd TCRB1 (DMA1 Count B)
FE008140 dd dd SARB2 (DMA2 Source address B)
FE008144 dd dd DARB2 (DMA2 Dest address B)
FE008148 dd dd TCRB2 (DMA2 Count B)
FE008150 dd dd SARB3 (DMA3 Source address B)
FE008154 dd dd DARB3 (DMA3 Dest address B)
FE008158 dd dd TCRB3 (DMA3 Count B)
FE009000 dw dw DMARS0 (DMA resource select 0)
FE009004 dw dw DMARS1 (DMA resource select 1)
FE009008 dw dw DMARS2 (DMA resource select 2)

MMU (Memory Manager)
FF000010 dd dd MMUCR (MMU Control)
FF000000 dd dd PTEH (MMU Page table entry high)
FF000004 dd dd PTEL (MMU Page table entry low)
FF000034 dd dd PTEA (MMU Page table entry assistance)
FF000008 dd dd TTB (MMU Translation table base)
FF00000C dd dd TEA (MMU TLB Exception address)
FF000070 dd dd PASCR (Physical address control)
FF000078 dd dd IRMCR (Instruction refetch inhibit control)
F2000000 01000000 dd ITLBADDRA (ITLB Address Array)
F3000000 00800000 dd ITLBDATAA1 (ITLB Data Array 1)
F3800000 00800000 dd ITLBDATAA2 (ITLB Data Array 2)
F6000000 00100000 dd UTLBADDRA (UTLB Address Array)
F7000000 00100000 dd UTLBDATAA1 (UTLB Data Array 1)
F7800000 00100000 dd UTLBDATAA2 (UTLB Data Array 2)
F6100000 00100000 dd PMBADDRA (PMB Address Array)
F7100000 00100000 dd PMBDATAA (PMB Data Array)

Cache (Cache control)
FF00001C dd dd CCR (Cache control)
F0000000 01000000 dd ICADDRA (Instruction Cache Address Array)
F1000000 01000000 dd ICDATAA (Instruction Cache Data Array)
F4000000 01000000 dd OCADDRA (Operand Cache Address Array)
F5000000 01000000 dd OCDATAA (Operand Cache Data Array)

BSC (Bus control)
FEC10048 dd dd RTCSR (Refresh timer control)
FEC1004C dd dd RTCNT (Refresh counter)
FEC10050 dd dd RTCOR (Refresh constant)
FEC10000 dd dd CMNCR (Bus Common control)
FEC10004 dd dd CS0BCR (Bus control for CS0)
FEC10008 dd dd CS2BCR (Bus control for CS2)
FEC1000C dd dd CS3BCR (Bus control for CS3)
FEC10010 dd dd CS4BCR (Bus control for CS4)
FEC10014 dd dd CS5ABCR (Bus control for CS5A)
FEC10018 dd dd CS5BBCR (Bus control for CS5B)
FEC1001C dd dd CS6ABCR (Bus control for CS6A)
FEC10020 dd dd CS6BBCR (Bus control for CS6B)
FEC10024 dd dd CS0WCR (Wait control for CS0)
FEC10028 dd dd CS2WCR (Wait control for CS2)
FEC1002C dd dd CS3WCR (Wait control for CS3)
FEC10030 dd dd CS4WCR (Wait control for CS4)
FEC10034 dd dd CS5AWCR (Wait control for CS5A)
FEC10038 dd dd CS5BWCR (Wait control for CS5B)
FEC1003C dd dd CS6AWCR (Wait control for CS6A)
FEC10040 dd dd CS6BWCR (Wait control for CS6B)
FEC10044 dd dd SDCR (SDRAM control)
FEC14000 00001000 db SDMR2 (SDRAM mode for CS2)
FEC15000 00001000 db SDMR3 (SDRAM mode for CS3)

Clock (Clock generation)
A4150000 dd dd FRQCR (Frequency control)
A4150008 dd dd FSICLKCR (FSI Clock control)
A415003C dd dd SPUCLKCR (SPU Clock control)
A4150010 dd dd DDCLKCR (DD Clock control)
A4150014 dd dd USBCLKCR (USB Clock control)
A4150024 dd dd PLLCR (PLL1 control)
A4150028 dd dd PLL2CR (PLL2 control)
A4150050 dd dd FLLFRQ (FLL Multiplication control)
A4150060 dd dd LSTATUS (Frequency change status)
A4150044 dd dd SSCGCR (Spread spectrum control)

RTC (Real-time clock)
A413FEC0 db db R64CNT (64-Hz counter)
A413FEC2 db db RSECCNT (Seconds counter)
A413FEC4 db db RMINCNT (Minutes counter)
A413FEC6 db db RHRCNT (Hours counter)
A413FEC8 db db RWKCNT (Weekday counter)
A413FECA db db RDAYCNT (Date counter)
A413FECC db db RMONCNT (Months counter)
A413FECE dw dw RYRCNT (Years counter)
A413FED0 db db RSECAR (Seconds alarm)
A413FED2 db db RMINAR (Minutes alarm)
A413FED4 db db RHRAR (Hours alarm)
A413FED6 db db RWKAR (Weekday alarm)
A413FED8 db db RDAYAR (Date alarm)
A413FEDA db db RMONAR (Months alarm)
A413FEE0 dw dw RYRAR (Years alarm)
A413FEDC db db RCR1 (RTC control 1)
A413FEDE db db RCR2 (RTC control 2)
A413FEE4 db db RCR3 (RTC control 3)

WDT (Watchdog timer)
A4520000 dw dw RWTCNT (Watchdog timer counter)
A4520004 dw dw RWTCSR (Watchdog control)

Power (Power-down modes)
A4150020 dd dd STBCR (Standby control)
A4150030 dd dd MSTPCR0 (Module stop 0)
A4150038 dd dd MSTPCR2 (Module stop 2)
A4150040 dd dd BAR (Boot address)

TMU0 (Timer unit 0)
A4490004 db db TSTR (Timer start)
A4490008 dd dd TCOR0 (Timer 0 constant)
A449000C dd dd TCNT0 (Timer 0 counter)
A4490010 dw dw TCR0 (Timer 0 control)

TMU1 (Timer unit 1)
A4490014 dd dd TCOR1 (Timer 1 constant)
A4490018 dd dd TCNT1 (Timer 1 counter)
A449001C dw dw TCR1 (Timer 1 control)

TMU2 (Timer unit 2)
A4490020 dd dd TCOR2 (Timer 2 constant)
A4490024 dd dd TCNT2 (Timer 2 counter)
A4490028 dw dw TCR2 (Timer 2 control)

CMT (Compare match timer)
A44A0000 dw dw CMSTR (Compare match timer start)
A44A0060 dw dw CMCSR (Compare match timer control)
A44A0064 dd dd CMCNT (Compare match timer counter)
A44A0068 dd dd CMCOR (Compare match timer constant)

SCIF (Serial communication)
A4410000 dw dw SCSMR (Serial Mode)
A4410004 db db SCBRR (Serial Bit rate)
A4410008 dw dw SCSCR (Serial Control)
A441000C db db SCFTDR (Serial Transmit data)
A4410010 dw dw SCFSR (Serial Status)
A4410014 db db SCFRDR (Serial Receive data)
A4410018 dw dw SCFCR (Serial FIFO control)
A441001C dw dw SCFDR (Serial FIFO count)
A4410024 dw dw SCLSR (Serial Line status)

IIC (I2C communication)
A4470000 db db ICDR (I2C bus data)
A4470004 db db ICCR (I2C bus control)
A4470008 db db ICSR (I2C bus status)
A447000C db db ICIC (I2C interrupt control)
A4470010 db db ICCL (I2C clock control low)
A4470014 db db ICCH (I2C clock control high)

USB (USB 2 control)
A4D80000 dw dw SYSCFG (System configuration control)
A4D80002 dw dw BUSWAIT (CPU bus wait setting)
A4D80004 dw dw SYSSTS (System configuration status)
A4D80008 dw dw DVSTCTR (Device status control)
A4D8000C dw dw TESTMODE (Test mode)
A4D80014 dd db CFIFO (CFIFO port)
A4D80018 dd db D0FIFO (D0FIFO port)
A4D8001C dd db D1FIFO (D1FIFO port)
A4D80020 dw dw CFIFOSEL (CFIFO port select)
A4D80022 dw dw CFIFOCTR (CFIFO port control)
A4D80028 dw dw D0FIFOSEL (D0FIFO port select)
A4D8002A dw dw D0FIFOCTR (D0FIFO port control)
A4D8002C dw dw D1FIFOSEL (D1FIFO port select)
A4D8002E dw dw D1FIFOCTR (D1FIFO port control)
A4D80030 dw dw INTENB0 (Interrupt enable 0)
A4D80036 dw dw BRDYENB (BRDY interrupt enable)
A4D80038 dw dw NRDYENB (NRDY interrupt enable)
A4D8003A dw dw BEMPENB (BEMP interrupt enable)
A4D8003C dw dw SOFCFG (SOF pin configuration)
A4D80040 dw dw INTSTS0 (Interrupt status 0)
A4D80046 dw dw BRDYSTS (BRDY interrupt status)
A4D80048 dw dw NRDYSTS (NRDY interrupt status)
A4D8004A dw dw BEMPSTS (BEMP interrupt status)
A4D8004C dw dw FRMNUM (Frame number)
A4D8004E dw dw UFRMNUM (mFrame number)
A4D80050 dw dw USBADDR (USB address)
A4D80054 dw dw USBREQ (USB request type)
A4D80056 dw dw USBVAL (USB request value)
A4D80058 dw dw USBINDX (USB request index)
A4D8005A dw dw USBLENG (USB request length)
A4D8005C dw dw DCPCFG (DCP configuration)
A4D8005E dw dw DCPMAXP (DCP max packet size)
A4D80060 dw dw DCPCTR (DCP control)
A4D80064 dw dw PIPESEL (Pipe window select)
A4D80068 dw dw PIPECFG (Pipe configuration)
A4D8006A dw dw PIPEBUF (Pipe buffer setting)
A4D8006C dw dw PIPEMAXP (Pipe max packet size)
A4D8006E dw dw PIPEPERI (Pipe cycle control)
A4D80070 dw dw PIPE1CTR (Pipe 1 control)
A4D80072 dw dw PIPE2CTR (Pipe 2 control)
A4D80074 dw dw PIPE3CTR (Pipe 3 control)
A4D80076 dw dw PIPE4CTR (Pipe 4 control)
A4D80078 dw dw PIPE5CTR (Pipe 5 control)
A4D8007A dw dw PIPE6CTR (Pipe 6 control)
A4D8007C dw dw PIPE7CTR (Pipe 7 control)
A4D8007E dw dw PIPE8CTR (Pipe 8 control)
A4D80080 dw dw PIPE9CTR (Pipe 9 control)
A4D80090 dw dw PIPE1TRE (Pipe 1 transaction counter enable)
A4D80092 dw dw PIPE1TRN (Pipe 1 transaction counter)
A4D80094 dw dw PIPE2TRE (Pipe 2 transaction counter enable)
A4D80096 dw dw PIPE2TRN (Pipe 2 transaction counter)
A4D80098 dw dw PIPE3TRE (Pipe 3 transaction counter enable)
A4D8009A dw dw PIPE3TRN (Pipe 3 transaction counter)
A4D8009C dw dw PIPE4TRE (Pipe 4 transaction counter enable)
A4D8009E dw dw PIPE4TRN (Pipe 4 transaction counter)
A4D800A0 dw dw PIPE5TRE (Pipe 5 transaction counter enable)
A4D800A2 dw dw PIPE5TRN (Pipe 5 transaction counter)
A40501D4 dw dw UPONCR (USB power control)

FLCTL (NAND Flash controller)
A4CC0000 dd dd FLCMNCR (Flash common control)
A4CC0004 dd dd FLCMDCR (Flash command control)
A4CC0008 dd dd FLCMCDR (Flash command code)
A4CC000C dd dd FLADR (Flash address)
A4CC003C dd dd FLADR2 (Flash address 2)
A4CC0014 dd dd FLDTCNTR (Flash data counter)
A4CC0010 dd dd FLDATAR (Flash data)
A4CC0018 dd dd FLINTDMACR (Flash Interrupt/DMA control)
A4CC001C dd dd FLBSYTMR (Flash Ready/busy timeout)
A4CC0020 dd dd FLBSYCNT (Flash Ready/busy timeout counter)
A4CC0024 dd dd FLDTFIFO (Flash data FIFO)
A4CC0050 00000010 dd FLDTFIFO2 (Flash data FIFO)
A4CC0028 dd dd FLECFIFO (Flash control code FIFO)
A4CC0060 00000010 dd FLECFIFO2 (Flash control code FIFO)
A4CC002C db db FLTRCR (Flash transfer control)
A4CC0080 dd dd FL4ECCRESULT1 (Flash ECC result 1)
A4CC0084 dd dd FL4ECCRESULT2 (Flash ECC result 2)
A4CC0088 dd dd FL4ECCRESULT3 (Flash ECC result 3)
A4CC008C dd dd FL4ECCRESULT4 (Flash ECC result 4)
A4CC0090 dd dd FL4ECCCR (Flash ECC control)
A4CC0094 dd dd FL4ECCCNT (Flash ECC error count)
A4CC0098 dd dd FLERRADR (Flash error address)
A4CC009C dd dd FLNANDON (NAND control)
A4CC1000 00000100 dd FLAPPBUF (Flash Auto Page Program address buffer)

ECC (ECC unit)
FD000000 dd dd ECCCR (ECC control)
FD000004 dd dd ECCSR (ECC status)
FD000008 dd dd ECCINTCR (ECC interrupt control)
FD00000C dd dd ECCRSTR (ECC reset)
FD000010 dd dd ECCERCNTR (ECC error count)
FD000080 dd dd ECCBWCNTR (ECC buffer write count)
FD000084 dd dd ECCERPOS1 (ECC error position 1)
FD000088 dd dd ECCERPOS2 (ECC error position 2)
FD00008C dd dd ECCERPOS3 (ECC error position 3)
FD000090 dd dd ECCERPOS4 (ECC error position 4)
FD000094 dd dd ECCERPOS5 (ECC error position 5)
FD000098 dd dd ECCERPOS6 (ECC error position 6)
FD00009C dd dd ECCERPOS7 (ECC error position 7)
FD0000A0 dd dd ECCERPOS8 (ECC error position 8)
FD0000A4 dd dd ECCERPOS9 (ECC error position 9)
FD0000A8 dd dd ECCERPOS10 (ECC error position 10)
FD0000AC dd dd ECCERPOS11 (ECC error position 11)
FD0000B0 dd dd ECCERPOS12 (ECC error position 12)
FD0000B4 dd dd ECCERPOS13 (ECC error position 13)
FD0000B8 dd dd ECCERPOS14 (ECC error position 14)
FD0000BC dd dd ECCERPOS15 (ECC error position 15)
FD001000 00000480 db ECCBUF (ECC buffer)

ADC (Analog/Digital converter)
A4610080 dw dw ADDRA (A/D A data)
A4610082 dw dw ADDRB (A/D B data)
A4610084 dw dw ADDRC (A/D C data)
A4610086 dw dw ADDRD (A/D D data)
A4610088 dw dw ADCSR (A/D Control/status)
A461008A dw dw ADCCSR (A/D Custom control)
A461008C dw dw ADCUST (A/D Control)
A461008E dw dw ADPCTL (A/D Port control)

Cmod (C-specification module)
A44C0000 dw dw DDCLKR0 (External CLK1 setting)
A44C0002 dw dw DDCLKR1 (External CLK2 setting)
A44C0004 dw dw DDCLKR2 (External CLK3 setting)
A44C0020 db db DDCK_CNTR (External clock control)
A44C0006 db db DDCS_CNTR (External CS control)
A44C0008 db db HIZ_CNTR (Interrupt pin level control)
A4CB0010 dw dw FASCR (BCD Calculation control)
A4CB0014 dd dd FASSRA (BCD Calculation source A)
A4CB0018 dd dd FASSRB (BCD Calculation source B)
A4CB001C dd dd FASDR (BCD Calculation result)
A44D0030 db db RTSTR0 (RTC Clock timer 0 start)
A44D003C db db RTCR0 (RTC Clock timer 0 control)
A44D0034 dd dd RTCOR0 (RTC Clock timer 0 constant)
A44D0038 dd dd RTCNT0 (RTC Clock timer 0 counter)
A44D0050 db db RTSTR1 (RTC Clock timer 1 start)
A44D005C db db RTCR1 (RTC Clock timer 1 control)
A44D0054 dd dd RTCOR1 (RTC Clock timer 1 constant)
A44D0058 dd dd RTCNT1 (RTC Clock timer 1 counter)
A44D0070 db db RTSTR2 (RTC Clock timer 2 start)
A44D007C db db RTCR2 (RTC Clock timer 2 control)
A44D0074 dd dd RTCOR2 (RTC Clock timer 2 constant)
A44D0078 dd dd RTCNT2 (RTC Clock timer 2 counter)
A44D0090 db db RTSTR3 (RTC Clock timer 3 start)
A44D009C db db RTCR3 (RTC Clock timer 3 control)
A44D0094 dd dd RTCOR3 (RTC Clock timer 3 constant)
A44D0098 dd dd RTCNT3 (RTC Clock timer 3 counter)
A44D00B0 db db RTSTR4 (RTC Clock timer 4 start)
A44D00BC db db RTCR4 (RTC Clock timer 4 control)
A44D00B4 dd dd RTCOR4 (RTC Clock timer 4 constant)
A44D00B8 dd dd RTCNT4 (RTC Clock timer 4 counter)
A44D00D0 db db RTSTR5 (RTC Clock timer 5 start)
A44D00DC db db RTCR5 (RTC Clock timer 5 control)
A44D00D4 dd dd RTCOR5 (RTC Clock timer 5 constant)
A44D00D8 dd dd RTCNT5 (RTC Clock timer 5 counter)

Cmod2A (C-specification module 2A)
A4CD0000 dd dd CHRMCTRL (Character extension operation control)
A4CD0004 dd dd CHRCOLOR (Character color specification)
A4CD0008 dd dd CHRRADDR (Character data read start address)
A4CD000C dd dd CHRSIZE (Character data read length)
A4CD0010 dd dd MSKRADDR (Mask data read start address)
A4CD0014 dd dd VRMWADDR (VRAM write start address)
A4CD0018 dd dd VRMWSBIT (VRAM write start bit)
A4CD001C dd dd VRMAREA (VRAM area)
A4CD0020 dd dd DESWADDR (Destination write start address)
A4CD0024 dd dd DESAREA (Destination area)
A4CD0028 dd dd DMAMCTRL (DMA data transfer operation control)
A4CD002C dd dd VRMRADDR (VRAM data read start address)
A4CD0030 dd dd VRMRSIZE (VRAM data read length)
A4CD0034 dd dd DDWPOINT1 (D/D-RAM write start pointer 1)
A4CD0038 dd dd DDWPOINT2 (D/D-RAM write start pointer 2)
A4CD003C dd dd DDWPOINT3 (D/D-RAM write start pointer 3)
A4CD0040 dd dd DDWPOINT4 (D/D-RAM write start pointer 4)
A4CD0044 dd dd DDWSIZE1 (D/D-RAM write length 1)
A4CD0048 dd dd DDWSIZE2 (D/D-RAM write length 2)
A4CD004C dd dd DDWSIZE3 (D/D-RAM write length 3)
A4CD0050 dd dd DDWSIZE4 (D/D-RAM write length 4)
A4CD0054 dd dd DDAREA1 (D/D-RAM area 1)
A4CD0058 dd dd DDAREA2 (D/D-RAM area 2)
A4CD005C dd dd DDAREA3 (D/D-RAM area 3)
A4CD0060 dd dd DDAREA4 (D/D-RAM area 4)
A4CD0064 dd dd LAYMCTRL (Layer operation control)

RAM (On-chip RAM)
E5007000 00002000 00000000 XRAM (On-chip DSP XRAM)
E5017000 00002000 00000000 YRAM (On-chip DSP YRAM)
E5200000 00001000 00000000 ILRAM (On-chip DSP ILRAM)
FD800000 00004000 00000000 RSRAM (On-chip RS RAM)
FF000074 dd dd RAMCR (On-chip memory control)
FF000050 dd dd XSA (X memory transfer source)
FF000054 dd dd YSA (Y memory transfer source)
FF000058 dd dd XDA (X memory transfer destination)
FF00005C dd dd YDA (Y memory transfer destination)
FF000060 dd dd XPR (X bus protection control)
FF000064 dd dd YPR (Y bus protection control)
FF000068 dd dd XEA (X bus exception address)
FF00006C dd dd YEA (Y bus exception address)

UBC (User break controller)
FF200000 dd dd CBR0 (Match condition setting 0)
FF200004 dd dd CRR0 (Match operation setting 0)
FF200008 dd dd CAR0 (Match address setting 0)
FF20000C dd dd CAMR0 (Match address mask setting 0)
FF200020 dd dd CBR1 (Match condition setting 1)
FF200024 dd dd CRR1 (Match operation setting 1)
FF200028 dd dd CAR1 (Match address setting 1)
FF20002C dd dd CAMR1 (Match address mask setting 1)
FF200030 dd dd CDR1 (Match data setting 1)
FF200034 dd dd CDMR1 (Match data mask setting 1)
FF200038 dd dd CETR1 (Execution count break 1)
FF200600 dd dd CCMFR (Channel match flag)
FF200620 dd dd CBCR (Break control)

HUDI (User debugging interface)
FC110000 dw dw SDIR (Debug instruction)
FC110008 dw dw SDDRH (Data register high)
FC11000A dw dw SDDRL (Data register low)
FC110018 dw dw SDINT (Interrupt source)

SDC (SD Card controller)
A4CF0000 dw dw SD_CMD (?)
A4CF0004 dw dw SD_ARG0 (?)
A4CF0006 dw dw SD_ARG1 (?)
A4CF0008 dw dw SD_STOP (?)
A4CF000A dw dw SD_SECCNT (?)
A4CF000C dw dw SD_RSP0 (?)
A4CF000E dw dw SD_RSP1 (?)
A4CF0010 dw dw SD_RSP2 (?)
A4CF0012 dw dw SD_RSP3 (?)
A4CF0014 dw dw SD_RSP4 (?)
A4CF0016 dw dw SD_RSP5 (?)
A4CF0018 dw dw SD_RSP6 (?)
A4CF001A dw dw SD_RSP7 (?)
A4CF001C dw dw SD_INFO1 (SD card information 1)
A4CF001E dw dw SD_INFO2 (?)
A4CF0020 dw dw SD_INFO1_MASK (?)
A4CF0022 dw dw SD_INFO2_MASK (?)
A4CF0024 dw dw SD_CLK_CNTL (?)
A4CF0026 dw dw SD_SIZE (?)
A4CF0028 dw dw SD_OPTION (?)
A4CF002C dw dw SD_ERR_STS1 (?)
A4CF002E dw dw SD_ERR_STS2 (?)
A4CF0030 dw dw SD_BUFO (?)
A4CF0034 dw dw SDIO_MODE (?)
A4CF0036 dw dw SDIO_INFO1 (?)
A4CF0038 dw dw SDIO_INFO1_MASK (?)
A4CF00D8 dw dw CC_EXT_MODE (?)
A4CF00E0 dw dw SOFT_RST (?)
A4CF00E2 dw dw VERSION (?)
A4CF00F0 dw dw EXT_SWAP (?)

MMC (MMC controller)
A4CA0000 dd dd CE_CMD_SET (Command setting)
A4CA0008 dd dd CE_ARG (Argument)
A4CA000C dd dd CE_ARG_CMD12 (Argument for CMD12)
A4CA0010 dd dd CE_CMD_CTRL (Command control)
A4CA0014 dd dd CE_BLOCK_SET (Transfer block setting)
A4CA0018 dd dd CE_CLK_CTRL (Clock control)
A4CA001C dd dd CE_BUF_ACC (Buffer access configuration)
A4CA0020 dd dd CE_RESP3 (Response 3)
A4CA0024 dd dd CE_RESP2 (Response 2)
A4CA0028 dd dd CE_RESP1 (Response 1)
A4CA002C dd dd CE_RESP0 (Response 0)
A4CA0030 dd dd CE_RESP_CMD12 (Response for CMD12)
A4CA0034 dd dd CE_DATA (Data)
A4CA003C dd dd CE_BOOT (Boot operation setting)
A4CA0040 dd dd CE_INT (Interrupt flag)
A4CA0044 dd dd CE_INT_EN (Enterrupt enable)
A4CA0048 dd dd CE_HOST_STS1 (Status 1)
A4CA004C dd dd CE_HOST_STS2 (Status 2)
A4CA007C dd dd CE_VERSION (Version)

SHway (Super Hyway Bus)
FF800018 dd dd PRLCKCR (LCK control)
FF800020 dd dd PRPRICR0 (PRI control 0)
FF800028 dd dd PRPRICR1 (PRI control 1)
FF800030 dd dd PRPRICR2 (PRI control 2)
FF800038 dd dd PRPRICR3 (PRI control 3)
FF800040 dd dd PRPRICR4 (PRI control 4)
FF800048 dd dd PRPRICR5 (PRI control 5)
A4530000 dd dd SHOCMCR (SHOC master control)
A4530004 dd dd SHOCMSR (SHOC master status)

KEY (Key interface unit)
A44B0000 dw dw KIUDATA0 (Key input data 0)
A44B0002 dw dw KIUDATA1 (Key input data 1)
A44B0004 dw dw KIUDATA2 (Key input data 2)
A44B0006 dw dw KIUDATA3 (Key input data 3)
A44B0008 dw dw KIUDATA4 (Key input data 4)
A44B000A dw dw KIUDATA5 (Key input data 5)
A44B000C dw dw KIUCNTREG (Scan control)
A44B000E dw dw KIAUTOFIXREG (Automatic key bounce setting)
A44B0010 dw dw KIUMODEREG (Scan mode setting)
A44B0012 dw dw KIUSTATEREG (Scan state)
A44B0014 dw dw KIUINTREG (Interrupt setting)
A44B0016 dw dw KIUWSETREG (Scan wait time setting)
A44B0018 dw dw KIUINTERVALREG (Scan interval time setting)
A44B001A dw dw KOUTPINSET (KOUT line function setting)
A44B001C dw dw KINPINSET (KIN line function setting)

MSIOF0 (Sync serial interface 0)
A4C40000 dd dd SITMDR1 (Transmit mode 1)
A4C40004 dd dd SITMDR2 (Transmit mode 2)
A4C40008 dd dd SITMDR3 (Transmit mode 3)
A4C40020 dw dw SITSCR (Transmit clock select)
A4C40010 dd dd SIRMDR1 (Receive mode 1)
A4C40014 dd dd SIRMDR2 (Receive mode 2)
A4C40018 dd dd SIRMDR3 (Receive mode 3)
A4C40024 dw dw SIRSCR (Receive clock select)
A4C40028 dd dd SICTR (Control)
A4C40030 dd dd SIFCTR (FIFO control)
A4C40040 dd dd SISTR (Status)
A4C40044 dd dd SIIER (Interrupt enable)
A4C40048 dd dd SITDR1 (Transmit control data 1)
A4C4004C dd dd SITDR2 (Transmit control data 2)
A4C40050 dd dd SITFDR (Transmit FIFO data)
A4C40058 dd dd SIRDR1 (Receive control data 1)
A4C4005C dd dd SIRDR2 (Receive control data 2)
A4C40060 dd dd SIRFDR (Receive FIFO data)

MSIOF1 (Sync serial interface 1)
A4C50000 dd dd SITMDR1 (Transmit mode 1)
A4C50004 dd dd SITMDR2 (Transmit mode 2)
A4C50008 dd dd SITMDR3 (Transmit mode 3)
A4C50020 dw dw SITSCR (Transmit clock select)
A4C50010 dd dd SIRMDR1 (Receive mode 1)
A4C50014 dd dd SIRMDR2 (Receive mode 2)
A4C50018 dd dd SIRMDR3 (Receive mode 3)
A4C50024 dw dw SIRSCR (Receive clock select)
A4C50028 dd dd SICTR (Control)
A4C50030 dd dd SIFCTR (FIFO control)
A4C50040 dd dd SISTR (Status)
A4C50044 dd dd SIIER (Interrupt enable)
A4C50048 dd dd SITDR1 (Transmit control data 1)
A4C5004C dd dd SITDR2 (Transmit control data 2)
A4C50050 dd dd SITFDR (Transmit FIFO data)
A4C50058 dd dd SIRDR1 (Receive control data 1)
A4C5005C dd dd SIRDR2 (Receive control data 2)
A4C50060 dd dd SIRFDR (Receive FIFO data)

SPU2 (Sound processing unit 2)
FE2FFC00 dd dd PBANKC0 (PRAM bank control 0)
FE2FFC04 dd dd PBANKC1 (PRAM bank control 1)
FE2FFC10 dd dd XBANKC0 (XRAM bank control 0)
FE2FFC14 dd dd XBANKC1 (XRAM bank control 1)
FE2FFC24 dd dd SPUSRST (SPU software reset)
FE2FFC28 dd dd SPUADR (SPU address)
FE2FFC2C dd dd ENDIAN (SHway endian)
FE2FFC40 dd dd GCOM0 (Global common 0)
FE2FFC44 dd dd GCOM1 (Global common 1)
FE2FFC48 dd dd GCOM2 (Global common 2)
FE2FFC4C dd dd GCOM3 (Global common 3)
FE2FFC50 dd dd GCOM4 (Global common 4)
FE2FFC54 dd dd GCOM5 (Global common 5)
FE2FFC58 dd dd GCOM6 (Global common 6)
FE2FFC5C dd dd GCOM7 (Global common 7)
FE2FFC80 dd dd DMABUF0 (Inter-DSP communication buffer 0)
FE2FFC84 dd dd DMABUF1 (Inter-DSP communication buffer 1)
FE2FFC88 dd dd DMABUF2 (Inter-DSP communication buffer 2)
FE2FFC8C dd dd DMABUF3 (Inter-DSP communication buffer 3)

SPU2DSP0 (DSP 0 for sound processing unit 2)
FE2FFD00 dd dd DSPRST (DSP full reset)
FE2FFD04 dd dd DSPCORERST (DSP core reset)
FE2FFD08 dd dd DSPHOLD (DSP hold)
FE2FFD0C dd dd DSPRESTART (DSP restart)
FE2FFD18 dd dd IEMASKC (CPU interrupt source mask)
FE2FFD1C dd dd IMASKC (CPU interrupt signal mask)
FE2FFD20 dd dd IEVENTC (CPU interrupt source)
FE2FFD24 dd dd IEMASKD (DSP interrupt source mask)
FE2FFD28 dd dd IMASKD (DSP interrupt signal mask)
FE2FFD2C dd dd IESETD (DSP interrupt set)
FE2FFD30 dd dd IECLRD (DSP interrupt clear)
FE2FFD34 dd dd OR (DMAC operation)
FE2FFD38 dd dd COM0 (CPU-DSP communication 0)
FE2FFD3C dd dd COM1 (CPU-DSP communication 1)
FE2FFD40 dd dd COM2 (CPU-DSP communication 2)
FE2FFD44 dd dd COM3 (CPU-DSP communication 3)
FE2FFD48 dd dd COM4 (CPU-DSP communication 4)
FE2FFD4C dd dd COM5 (CPU-DSP communication 5)
FE2FFD50 dd dd COM6 (CPU-DSP communication 6)
FE2FFD54 dd dd COM7 (CPU-DSP communication 7)
FE2FFD58 dd dd BTADRU (Bus-through address high)
FE2FFD5C dd dd BTADRL (Bus-through address low)
FE2FFD60 dd dd WDATU (Bus-through write data high)
FE2FFD64 dd dd WDATL (Bus-through write data low)
FE2FFD68 dd dd RDATU (Bus-through read data high)
FE2FFD6C dd dd RDATL (Bus-through read data low)
FE2FFD70 dd dd BTCTRL (Bus-through mode control)
FE2FFD74 dd dd SPUSTS (SPU status)
FE2FFE00 dd dd SBAR0 (Source base address 0)
FE2FFE04 dd dd SAR0 (Source address 0)
FE2FFE08 dd dd DBAR0 (Destination base address 0)
FE2FFE0C dd dd DAR0 (Destination address 0)
FE2FFE10 dd dd TCR0 (Transfer count 0)
FE2FFE14 dd dd SHPRI0 (SHway priority 0)
FE2FFE18 dd dd CHCR0 (Channel control 0)
FE2FFE20 dd dd SBAR1 (Source base address 1)
FE2FFE24 dd dd SAR1 (Source address 1)
FE2FFE28 dd dd DBAR1 (Destination base address 1)
FE2FFE2C dd dd DAR1 (Destination address 1)
FE2FFE30 dd dd TCR1 (Transfer count 1)
FE2FFE34 dd dd SHPRI1 (SHway priority 1)
FE2FFE38 dd dd CHCR1 (Channel control 1)
FE2FFE40 dd dd SBAR2 (Source base address 2)
FE2FFE44 dd dd SAR2 (Source address 2)
FE2FFE48 dd dd DBAR2 (Destination base address 2)
FE2FFE4C dd dd DAR2 (Destination address 2)
FE2FFE50 dd dd TCR2 (Transfer count 2)
FE2FFE54 dd dd SHPRI2 (SHway priority 2)
FE2FFE58 dd dd CHCR2 (Channel control 2)
FE2FFE80 dd dd LSA0 (Loop start address 0)
FE2FFE84 dd dd LEA0 (Loop end address 0)
FE2FFE90 dd dd LSA1 (Loop start address 1)
FE2FFE94 dd dd LEA1 (Loop end address 1)
FE2FFEA0 dd dd LSA2 (Loop start address 2)
FE2FFEA4 dd dd LEA2 (Loop end address 2)

SPU2DSP1 (DSP 1 for sound processing unit 2)
FE3FFD00 dd dd DSPRST (DSP full reset)
FE3FFD04 dd dd DSPCORERST (DSP core reset)
FE3FFD08 dd dd DSPHOLD (DSP hold)
FE3FFD0C dd dd DSPRESTART (DSP restart)
FE3FFD18 dd dd IEMASKC (CPU interrupt source mask)
FE3FFD1C dd dd IMASKC (CPU interrupt signal mask)
FE3FFD20 dd dd IEVENTC (CPU interrupt source)
FE3FFD24 dd dd IEMASKD (DSP interrupt source mask)
FE3FFD28 dd dd IMASKD (DSP interrupt signal mask)
FE3FFD2C dd dd IESETD (DSP interrupt set)
FE3FFD30 dd dd IECLRD (DSP interrupt clear)
FE3FFD34 dd dd OR (DMAC operation)
FE3FFD38 dd dd COM0 (CPU-DSP communication 0)
FE3FFD3C dd dd COM1 (CPU-DSP communication 1)
FE3FFD40 dd dd COM2 (CPU-DSP communication 2)
FE3FFD44 dd dd COM3 (CPU-DSP communication 3)
FE3FFD48 dd dd COM4 (CPU-DSP communication 4)
FE3FFD4C dd dd COM5 (CPU-DSP communication 5)
FE3FFD50 dd dd COM6 (CPU-DSP communication 6)
FE3FFD54 dd dd COM7 (CPU-DSP communication 7)
FE3FFD58 dd dd BTADRU (Bus-through address high)
FE3FFD5C dd dd BTADRL (Bus-through address low)
FE3FFD60 dd dd WDATU (Bus-through write data high)
FE3FFD64 dd dd WDATL (Bus-through write data low)
FE3FFD68 dd dd RDATU (Bus-through read data high)
FE3FFD6C dd dd RDATL (Bus-through read data low)
FE3FFD70 dd dd BTCTRL (Bus-through mode control)
FE3FFD74 dd dd SPUSTS (SPU status)
FE3FFE00 dd dd SBAR0 (Source base address 0)
FE3FFE04 dd dd SAR0 (Source address 0)
FE3FFE08 dd dd DBAR0 (Destination base address 0)
FE3FFE0C dd dd DAR0 (Destination address 0)
FE3FFE10 dd dd TCR0 (Transfer count 0)
FE3FFE14 dd dd SHPRI0 (SHway priority 0)
FE3FFE18 dd dd CHCR0 (Channel control 0)
FE3FFE20 dd dd SBAR1 (Source base address 1)
FE3FFE24 dd dd SAR1 (Source address 1)
FE3FFE28 dd dd DBAR1 (Destination base address 1)
FE3FFE2C dd dd DAR1 (Destination address 1)
FE3FFE30 dd dd TCR1 (Transfer count 1)
FE3FFE34 dd dd SHPRI1 (SHway priority 1)
FE3FFE38 dd dd CHCR1 (Channel control 1)
FE3FFE40 dd dd SBAR2 (Source base address 2)
FE3FFE44 dd dd SAR2 (Source address 2)
FE3FFE48 dd dd DBAR2 (Destination base address 2)
FE3FFE4C dd dd DAR2 (Destination address 2)
FE3FFE50 dd dd TCR2 (Transfer count 2)
FE3FFE54 dd dd SHPRI2 (SHway priority 2)
FE3FFE58 dd dd CHCR2 (Channel control 2)
FE3FFE80 dd dd LSA0 (Loop start address 0)
FE3FFE84 dd dd LEA0 (Loop end address 0)
FE3FFE90 dd dd LSA1 (Loop start address 1)
FE3FFE94 dd dd LEA1 (Loop end address 1)
FE3FFEA0 dd dd LSA2 (Loop start address 2)
FE3FFEA4 dd dd LEA2 (Loop end address 2)

SPU2RAM (Sound processing unit 2 RAM)
FE200000 00028000 dd PRAM0 (DSP0 Program RAM)
FE240000 00038000 dd XRAM0 (DSP0 XRAM)
FE280000 0000A000 dd YRAM0 (DSP0 YRAM)
FE300000 00028000 dd PRAM1 (DSP1 Program RAM)
FE340000 00038000 dd XRAM1 (DSP1 XRAM)
FE380000 0000A000 dd YRAM1 (DSP1 YRAM)

FSI (FIFO serial interface)
FE3C0000 dd dd A_DO_FMT (A output serial format)
FE3C0004 dd dd A_DOFF_CTL (A output FIFO control)
FE3C0008 dd dd A_DOFF_ST (A output FIFO status)
FE3C000C dd dd A_DI_FMT (A input serial format)
FE3C0010 dd dd A_DIFF_CTL (A input FIFO control)
FE3C0014 dd dd A_DIFF_ST (A input FIFO status)
FE3C0018 dd dd A_CKG1 (A clock set 1)
FE3C001C dd dd A_CKG2 (A clock set 2)
FE3C0020 dd dd A_DIDT (A read data)
FE3C0024 dd dd A_DODT (A write data)
FE3C0028 dd dd A_MUTE_ST (A mute state)
FE3C0040 dd dd B_DO_FMT (B output serial format)
FE3C0044 dd dd B_DOFF_CTL (B output FIFO control)
FE3C0048 dd dd B_DOFF_ST (B output FIFO status)
FE3C004C dd dd B_DI_FMT (B input serial format)
FE3C0050 dd dd B_DIFF_CTL (B input FIFO control)
FE3C0054 dd dd B_DIFF_ST (B input FIFO status)
FE3C0058 dd dd B_CKG1 (B clock set 1)
FE3C005C dd dd B_CKG2 (B clock set 2)
FE3C0060 dd dd B_DIDT (B read data)
FE3C0064 dd dd B_DODT (B write data)
FE3C0068 dd dd B_MUTE_ST (B mute state)
FE3C0200 dd dd INT_ST (Interrupt state)
FE3C0204 dd dd IEMSK (Interrupt source mask)
FE3C0208 dd dd IMSK (Interrupt signal mask)
FE3C020C dd dd MUTE (Mute set)
FE3C0210 dd dd CLK_RST (Clock reset)
FE3C0214 dd dd SOFT_RST (Software reset)
FE3C0218 dd dd FIFO_SZ (FIFO size)
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Calculators: Casio fx-7400GII, Casio fx-7400GII (SH4), Casio fx-9750 G II, Casio fx-9750 G II (SH4), Casio fx-9860G, Casio fx-9860 G SD, Casio fx-9860G Slim, Casio fx-9860 GII SD, Casio fx-9860 GII SD Power Graphic 2, Casio Classpad 330 plus, Casio fx-CG 20, Casio Classpad fx-cp400, Casio fx-CG 50

Re: No FPU in fx-9860G II?

Postby SimonLothar » Sun Feb 05, 2017 5:46 pm

Here the list of SH7337/SH7355 registers.
With the interrupt priority- and port control-registers I enhanced the bit-incompatibilities compared to the SH7705 MPU.
SH7337 SH7355 registers: Show
FFFFFFD0 dd dd TRA (Trap event)
FFFFFFD4 dd dd EXPEVT (Exception event)

INT (Interrupt)
FFFFFEE2 dw dw IPRA (Interrupt priority A) [0xFFFF]
FFFFFEE4 dw dw IPRB (Interrupt priority B) [0xFF00]
A4000016 dw dw IPRC (Interrupt priority C) [0xFFFF]
A4000018 dw dw IPRD (Interrupt priority D) [0xFF00]
A400001A dw dw IPRE (Interrupt priority E) [0xF0FF]
A4080000 dw dw IPRF (Interrupt priority F) [0x00FF]
A4080002 dw dw IPRG (Interrupt priority G) [0xFF00]
A4080004 dw dw IPRH (Interrupt priority H) [0xFFFF]
A4080006 dw dw IPRI (Interrupt priority I) [0x00F0]
FFFFFEE0 dw dw ICR0 (Interrupt control 0)
A4000010 dw dw ICR1 (Interrupt control 1)
A4000012 dw dw ICR2 (Interrupt control 2)
A4000014 dw dw PINTER (PINT enable)
A4000004 db db IRR0 (Interrupt request 0)
A4000006 db db IRR1 (Interrupt request 1)
A4000008 db db IRR2 (Interrupt request 2)
FFFFFFD8 dd dd INTEVT (Interrupt event)
A4000000 dd dd INTEVT2 (Interrupt event 2)

DMA (DMA Controller)
A4000020 dd dd SAR0 (DMA0 Source address)
A4000024 dd dd DAR0 (DMA0 Dest address)
A4000028 dd dd DMATCR0 (DMA0 Count)
A400002C dd dd CHCR0 (DMA0 Control)
A4000030 dd dd SAR1 (DMA1 Source address)
A4000034 dd dd DAR1 (DMA1 Dest address)
A4000038 dd dd DMATCR1 (DMA1 Count)
A400003C dd dd CHCR1 (DMA1 Control)
A4000040 dd dd SAR2 (DMA2 Source address)
A4000044 dd dd DAR2 (DMA2 Dest address)
A4000048 dd dd DMATCR2 (DMA2 Count)
A400004C dd dd CHCR2 (DMA2 Control)
A4000050 dd dd SAR3 (DMA3 Source address)
A4000054 dd dd DAR3 (DMA3 Dest address)
A4000058 dd dd DMATCR3 (DMA3 Count)
A400005C dd dd CHCR3 (DMA3 Control)
A4000060 dw dw DMAOR (DMA Operation)
A4090000 dw dw DMARS0 (DMA resource select 0)
A4090004 dw dw DMARS1 (DMA resource select 1)

MMU (Memory Manager)
FFFFFFE0 dd dd MMUCR (MMU Control)
FFFFFFF0 dd dd PTEH (MMU Page table entry high)
FFFFFFF4 dd dd PTEL (MMU Page table entry low)
FFFFFFF8 dd dd TTB (MMU Translation table base)
FFFFFFFC dd dd TEA (MMU TLB Exception address)
F2000000 01000000 dd TLBADDRA (TLB Address Array)
F3000000 01000000 dd TLBDATAA (TLB Data Array)

Cache (Cache control)
FFFFFFEC dd dd CCR1 (Cache control 1)
A40000B0 dd dd CCR2 (Cache control 2)
A40000B4 dd dd CCR3 (Cache control 3)
F0000000 01000000 dd CADDRA (Cache Address Array)
F1000000 01000000 dd CDATAA (Cache Data Array)

BSC (Bus control)
A4FD0048 dd dd RTCSR (Refresh timer control)
A4FD004C dd dd RTCNT (Refresh counter)
A4FD0050 dd dd RTCOR (Refresh constant)
A4FD0000 dd dd CMNCR (Bus Common control)
A4FD0004 dd dd CS0BCR (Bus control for CS0)
A4FD0008 dd dd CS2BCR (Bus control for CS2)
A4FD000C dd dd CS3BCR (Bus control for CS3)
A4FD0010 dd dd CS4BCR (Bus control for CS4)
A4FD0014 dd dd CS5ABCR (Bus control for CS5A)
A4FD0018 dd dd CS5BBCR (Bus control for CS5B)
A4FD001C dd dd CS6ABCR (Bus control for CS6A)
A4FD0020 dd dd CS6BBCR (Bus control for CS6B)
A4FD0024 dd dd CS0WCR (Wait control for CS0)
A4FD0028 dd dd CS2WCR (Wait control for CS2)
A4FD002C dd dd CS3WCR (Wait control for CS3)
A4FD0030 dd dd CS4WCR (Wait control for CS4)
A4FD0034 dd dd CS5AWCR (Wait control for CS5A)
A4FD0038 dd dd CS5BWCR (Wait control for CS5B)
A4FD003C dd dd CS6AWCR (Wait control for CS6A)
A4FD0040 dd dd CS6BWCR (Wait control for CS6B)
A4FD0044 dd dd SDCR (SDRAM control)
A4FD4000 00001000 db SDMR2 (SDRAM mode for CS2)
A4FD5000 00001000 db SDMR3 (SDRAM mode for CS3)

Clock (Clock generation)
FFFFFF80 dw dw FRQCR (Frequency control)
A40A0008 db db UCLKCR (USB Clock control)
FFFFFF84 dw dw WTCNT (Watchdog timer counter)
FFFFFF86 dw dw WTCSR (Watchdog control)

Power (Power-down modes)
FFFFFF82 db db STBCR (Standby control)
FFFFFF88 db db STBCR2 (Standby control 2)
A40A0000 db db STBCR3 (Standby control 3)
A40A0004 db db STBCR4 (Standby control 4)

TMU0 (Timer unit 0)
FFFFFE92 db db TSTR (Timer start)
FFFFFE94 dd dd TCOR0 (Timer 0 constant)
FFFFFE98 dd dd TCNT0 (Timer 0 counter)
FFFFFE9C dw dw TCR0 (Timer 0 control)

TMU1 (Timer unit 1)
FFFFFEA0 dd dd TCOR1 (Timer 1 constant)
FFFFFEA4 dd dd TCNT1 (Timer 1 counter)
FFFFFEA8 dw dw TCR1 (Timer 1 control)

TMU2 (Timer unit 2)
FFFFFEAC dd dd TCOR2 (Timer 2 constant)
FFFFFEB0 dd dd TCNT2 (Timer 2 counter)
FFFFFEB4 dw dw TCR2 (Timer 2 control)
FFFFFEB8 dd dd TCPR2 (Timer 2 capture)

CMT (Compare match timer)
A4000070 dw dw CMSTR (Compare match timer start)
A4000074 dw dw CMCSR (Compare match timer control)
A4000078 dw dw CMCNT (Compare match timer counter)
A400007C dw dw CMCOR (Compare match timer constant)

TPU0 (Timer pulse unit 0)
A4490000 dw dw TPSTR (Timer pulse start)
A4490010 dw dw TCR_0 (Timer pulse 0 control)
A4490014 dw dw TMDR_0 (Timer pulse 0 mode)
A4490018 dw dw TIOR_0 (Timer pulse 0 I/O control)
A449001C dw dw TIER_0 (Timer pulse 0 interrupt enable)
A4490020 dw dw TSR_0 (Timer pulse 0 status)
A4490024 dw dw TCNT_0 (Timer pulse 0 counter)
A4490028 dw dw TGRA_0 (Timer pulse 0 general register A)
A449002C dw dw TGRB_0 (Timer pulse 0 general register B)
A4490030 dw dw TGRC_0 (Timer pulse 0 general register C)
A4490034 dw dw TGRD_0 (Timer pulse 0 general register D)

TPU1 (Timer pulse unit 1)
A4490050 dw dw TCR_1 (Timer pulse 1 control)
A4490054 dw dw TMDR_1 (Timer pulse 1 mode)
A4490058 dw dw TIOR_1 (Timer pulse 1 I/O control)
A449005C dw dw TIER_1 (Timer pulse 1 interrupt enable)
A4490060 dw dw TSR_1 (Timer pulse 1 status)
A4490064 dw dw TCNT_1 (Timer pulse 1 counter)
A4490068 dw dw TGRA_1 (Timer pulse 1 general register A)
A449006C dw dw TGRB_1 (Timer pulse 1 general register B)
A4490070 dw dw TGRC_1 (Timer pulse 1 general register C)
A4490074 dw dw TGRD_1 (Timer pulse 1 general register D)

TPU2 (Timer pulse unit 2)
A4490090 dw dw TCR_2 (Timer pulse 2 control)
A4490094 dw dw TMDR_2 (Timer pulse 2 mode)
A4490098 dw dw TIOR_2 (Timer pulse 2 I/O control)
A449009C dw dw TIER_2 (Timer pulse 2 interrupt enable)
A44900A0 dw dw TSR_2 (Timer pulse 2 status)
A44900A4 dw dw TCNT_2 (Timer pulse 2 counter)
A44900A8 dw dw TGRA_2 (Timer pulse 2 general register A)
A44900AC dw dw TGRB_2 (Timer pulse 2 general register B)
A44900B0 dw dw TGRC_2 (Timer pulse 2 general register C)
A44900B4 dw dw TGRD_2 (Timer pulse 2 general register D)

TPU3 (Timer pulse unit 3)
A44900D0 dw dw TCR_3 (Timer pulse 3 control)
A44900D4 dw dw TMDR_3 (Timer pulse 3 mode)
A44900D8 dw dw TIOR_3 (Timer pulse 3 I/O control)
A44900DC dw dw TIER_3 (Timer pulse 3 interrupt enable)
A44900E0 dw dw TSR_3 (Timer pulse 3 status)
A44900E4 dw dw TCNT_3 (Timer pulse 3 counter)
A44900E8 dw dw TGRA_3 (Timer pulse 3 general register A)
A44900EC dw dw TGRB_3 (Timer pulse 3 general register B)
A44900F0 dw dw TGRC_3 (Timer pulse 3 general register C)
A44900F4 dw dw TGRD_3 (Timer pulse 3 general register D)

RTC (Real-time clock)
FFFFFEC0 db db R64CNT (64-Hz counter)
FFFFFEC2 db db RSECCNT (Seconds counter)
FFFFFEC4 db db RMINCNT (Minutes counter)
FFFFFEC6 db db RHRCNT (Hours counter)
FFFFFEC8 db db RWKCNT (Weekday counter)
FFFFFECA db db RDAYCNT (Date counter)
FFFFFECC db db RMONCNT (Months counter)
FFFFFECE dw dw RYRCNT (Years counter)
FFFFFED0 db db RSECAR (Seconds alarm)
FFFFFED2 db db RMINAR (Minutes alarm)
FFFFFED4 db db RHRAR (Hours alarm)
FFFFFED6 db db RWKAR (Weekday alarm)
FFFFFED8 db db RDAYAR (Date alarm)
FFFFFEDA db db RMONAR (Months alarm)
A413FEE0 dw dw RYRAR (Years alarm)
FFFFFEDC db db RCR1 (RTC control 1)
FFFFFEDE db db RCR2 (RTC control 2)
A413FEE4 db db RCR3 (RTC control 3)

SCIF2 (Serial communication 2)
A4410000 dw dw SCSMR2 (Serial 2 Mode)
A4410004 db db SCBRR2 (Serial 2 Bit rate)
A4410008 dw dw SCSCR2 (Serial 2 Control)
A4410020 db db SCFTDR2 (Serial 2 Transmit data)
A4410010 dw dw SCFER2 (Serial 2 FIFO error count)
A4410014 dw dw SCSSR2 (Serial 2 Status)
A4410024 db db SCFRDR2 (Serial 2 Receive data)
A4410018 dw dw SCFCR2 (Serial 2 FIFO control)
A441001C dw dw SCFDR2 (Serial 2 FIFO count)
A441000C db db SCTDSR2 (Serial 2 Transmit data stop)

USB (USB control)
A4480018 db db IFR0 (USB Interrupt flag 0)
A448001C db db IFR1 (USB Interrupt flag 1)
A4480044 db db ISR0 (USB Interrupt select 0)
A4480048 db db ISR1 (USB Interrupt select 1)
A4480034 db db IER0 (USB Interrupt enable 0)
A4480038 db db IER1 (USB Interrupt enable 1)
A4480000 db db EPDR0i (Endpoint 0 Transmit)
A4480004 db db EPDR0o (Endpoint 0 Receive)
A4480008 db db EPDR0s (Endpoint 0 Receive setup)
A448000C db db EPDR1 (Endpoint 1 Receive)
A4480010 db db EPDR2 (Endpoint 2 Transmit)
A4480014 db db EPDR3 (Endpoint 3 Receive)
A4480028 db db EPSZ0o (Endpoint 0 Receive data size)
A448003C db db EPSZ1 (Endpoint 1 Receive data size)
A4480020 db db TRG (USB Trigger)
A448002C db db DASTS (USB Data status)
A4480024 db db FCLR (USB FIFO clear)
A4480040 db db DMAR (USB DMA setting)
A4480030 db db EPSTL (USB Endpoint stall)
A4480060 db db XVERCR (USB Tranceiver control)

FLCTL (NAND Flash controller)
A44B0000 dd dd FLCMNCR (Flash common control)
A44B0004 dd dd FLCMDCR (Flash command control)
A44B0008 dd dd FLCMCDR (Flash command code)
A44B000C dd dd FLADR (Flash address)
A44B0014 dd dd FLDTCNTR (Flash data counter)
A44B0010 dd dd FLDATAR (Flash data)
A44B0018 dd dd FLINTDMACR (Flash Interrupt/DMA control)
A44B001C dd dd FLBSYTMR (Flash Ready/busy timeout)
A44B0020 dd dd FLBSYCNT (Flash Ready/busy timeout counter)
A44B0024 dd dd FLDTFIFO (Flash data FIFO)
A44B0028 dd dd FLECFIFO (Flash control code FIFO)
A44B002C db db FLTRCR (Flash transfer control)

AIF (Audio controller)
A4500000 db db AIFAUDMDR (Audio interface mode)
A4500001 db db AIFLATTR (Left channel output level)
A4500002 db db AIFRATTR (Right channel output level)
A4500008 dw dw AIFRSTR (Audio interface reset)
A450000A dw dw AIFDTCR (Audio transfer control)
A450000C dw dw AIFSTR (Audio transfer status)
A450000E dw dw AIFDR (Audio data register)
A4500003 db db AIFOPSR0 (Audio option select 0)
A4500004 db db AIFOPSR1 (Audio option select 1)

PFC (Port function control)
A4000100 dw dw PACR (Port A Control) [0xFFFF]
A4000102 dw dw PBCR (Port B Control) [0xFFFF]
A4000104 dw dw PCCR (Port C Control) [0xFFFF]
A4000106 dw dw PDCR (Port D Control) [0xFFFF]
A4000108 dw dw PECR (Port E Control) [0xFFCF]
A400010A dw dw PFCR (Port F Control) [0xFFFF]
A400010C dw dw PGCR (Port G Control) [0xFFFF]
A400010E dw dw PHCR (Port H Control) [0x3CFF]
A4000110 dw dw PJCR (Port J Control) [0xFFFF]
A4000112 dw dw PKCR (Port K Control) [0xFFFF]
A4000114 dw dw PLCR (Port L Control) [0x00FF/0x0FFF] (can be used to distinguish between SH7337 and SH7355)
A4000118 dw dw PMCR (Port M Control) [0x03FF]
A400011A dw dw PNCR (Port N Control) [0xFFFF]
A4000116 dw dw SCPCR (SC Port control) [0x000F]
A4050144 db db PCCR2 (Port C control 2) [0xB9]
A4050146 db db PDCR2 (Port D control 2) [0x80]
A4050148 db db PECR2 (Port E control 2) [0x70]
A405014A db db PFCR2 (Port F control 2) [0x0F]
A4050150 db db PJCR2 (Port J control 2) [0x1C]
A405015A db db PNCR2 (Port N control 2) [0x7F]
A405015C db db EPINTER (Extension PINT interrupt enable)
A4050156 db db SCPCR2 (SC Port control 2)
A4000180 dw dw HIZDTCR (Data pin Hi-Z control)
A4000184 db db HIZSDCR (SD pin Hi-Z control)
A4000188 dw dw DRVCR (Buffer drive control)
A400011C db db PULDTCR (Data pin pull-up/down control)
A4050161 db db PULACR (Port A pull-up/down control)
A4050163 db db PULBCR (Port B pull-up/down control)
A4050164 db db PUDCSR (Port C pull-up/down select)
A4050165 db db PULCCR (Port C pull-up/down control)
A4050166 db db PUDDSR (Port D pull-up/down select)
A4050167 db db PULDCR (Port D pull-up/down control)
A4050168 db db PUDESR (Port E pull-up/down select)
A4050169 db db PULECR (Port E pull-up/down control)
A405016A db db PUDFSR (Port F pull-up/down select)
A405016B db db PULFCR (Port F pull-up/down control)
A405016C db db PUDGSR (Port G pull-up/down select)
A405016D db db PULGCR (Port G pull-up/down control)
A405016E db db PUDHSR (Port H pull-up/down select)
A405016F db db PULHCR (Port H pull-up/down control)
A4050170 db db PUDJSR (Port J pull-up/down select)
A4050171 db db PULJCR (Port J pull-up/down control)
A4050172 db db PUDKSR (Port K pull-up/down select)
A4050173 db db PULKCR (Port K pull-up/down control)
A4050178 db db PUDMSR (Port M pull-up/down select)
A4050179 db db PULMCR (Port M pull-up/down control)
A405017A db db PUDNSR (Port N pull-up/down select)
A405017B db db PULNCR (Port N pull-up/down control)
A4050176 db db PUDSCSR (SC Port pull-up/down select)
A4050177 db db PULSCCR (SC Port pull-up/down control)

IO (Port I/O)
A4000120 db db PADR (Port A data)
A4000122 db db PBDR (Port B data)
A4000124 db db PCDR (Port C data)
A4000126 db db PDDR (Port D data)
A4000128 db db PEDR (Port E data)
A400012A db db PFDR (Port F data)
A400012C db db PGDR (Port G data)
A400012E db db PHDR (Port H data)
A4000130 db db PJDR (Port J data)
A4000132 db db PKDR (Port K data)
A4000134 db db PLDR (Port L data)
A4000138 db db PMDR (Port M data)
A400013A db db PNDR (Port N data)
A4000136 db db SCPDR (SC Port data)

ADC (Analog/Digital converter)
A4000080 dw dw ADDRA (A/D A data)
A4000082 dw dw ADDRB (A/D B data)
A4000084 dw dw ADDRC (A/D C data)
A4000086 dw dw ADDRD (A/D D data)
A4000088 dw dw ADCSR (A/D Control/status)
A400008A dw dw ADCCSR (A/D Custom control)
A400008C dw dw ADCUST (A/D Control)
A400008E dw dw ADPCTL (A/D Port control)

Cmod (C-specification module)
A44C0000 dw dw DDCLKR0 (External CLK1 setting)
A44C0002 dw dw DDCLKR1 (External CLK2 setting)
A44C0004 dw dw DDCLKR2 (External CLK3 setting)
A44C0020 db db DDCK_CNTR (External clock control)
A44C0006 db db DDCS_CNTR (External CS control)
A44C0008 db db HIZ_CNTR (Interrupt pin level control)
A44C0010 dw dw FASCR (BCD Calculation control)
A44C0014 dd dd FASSRA (BCD Calculation source A)
A44C0018 dd dd FASSRB (BCD Calculation source B)
A44C001C dd dd FASDR (BCD Calculation result)
A405015E db db SCOLCR (SC Output level control)
A44C0030 db db RTCSTR (RTC Clock timer start)
A44C003C db db RTCCR (RTC Clock timer control)
A44C0034 dd dd RTCCOR (RTC Clock timer constant)
A44C0038 dd dd RTCCNT (RTC Clock timer counter)
A40001AC db db OPCR (Output pin control)

RAM (On-chip RAM)
A5600000 00004000 00000000 RAM (On-chip RAM)

UBC (User break controller)
FFFFFFB0 dd dd BARA (Break address A)
FFFFFFB4 dd dd BAMRA (Break address mask A)
FFFFFFB8 dw dw BBRA (Break bus cycle A)
FFFFFFA0 dd dd BARB (Break address B)
FFFFFFA4 dd dd BAMRB (Break address mask B)
FFFFFFA8 dw dw BBRB (Break bus cycle B)
FFFFFF90 dd dd BDRB (Break data B)
FFFFFF94 dd dd BDMRB (Break data mask B)
FFFFFF98 dd dd BRCR (Break control)
FFFFFF9C dw dw BETR (Break execution count)
FFFFFFAC dd dd BRSR (Branch source)
FFFFFFBC dd dd BRDR (Branch destination)
FFFFFFE4 db db BASRA (Break ASID A)
FFFFFFE8 db db BASRB (Break ASID B)

HUDI (User debugging interface)
A4000200 dw dw SDIR (Debug instruction)
A4000214 dd dd SDID (Debug ID)

SDC (SD Card controller)
A4550000 dw dw SD_CMD (?)
A4550004 dw dw SD_ARG0 (?)
A4550006 dw dw SD_ARG1 (?)
A4550008 dw dw SD_STOP (?)
A455000A dw dw SD_SECCNT (?)
A455000C dw dw SD_RSP0 (?)
A455000E dw dw SD_RSP1 (?)
A4550010 dw dw SD_RSP2 (?)
A4550012 dw dw SD_RSP3 (?)
A4550014 dw dw SD_RSP4 (?)
A4550016 dw dw SD_RSP5 (?)
A4550018 dw dw SD_RSP6 (?)
A455001A dw dw SD_RSP7 (?)
A455001C dw dw SD_INFO1 (SD card information 1)
A455001E dw dw SD_INFO2 (?)
A4550020 dw dw SD_INFO1_MASK (?)
A4550022 dw dw SD_INFO2_MASK (?)
A4550024 dw dw SD_CLK_CNTL (?)
A4550026 dw dw SD_SIZE (?)
A4550028 dw dw SD_OPTION (?)
A455002C dw dw SD_ERR_STS1 (?)
A455002E dw dw SD_ERR_STS2 (?)
A4550030 dw dw SD_BUFO (?)
A4550034 dw dw SDIO_MODE (?)
A4550036 dw dw SDIO_INFO1 (?)
A4550038 dw dw SDIO_INFO1_MASK (?)
A45500D8 dw dw CC_EXT_MODE (?)
A45500E0 dw dw SOFT_RST (?)
A45500E2 dw dw VERSION (?)
A45500F0 dw dw EXT_SWAP (?)
 
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Calculators: Casio fx-7400GII, Casio fx-7400GII (SH4), Casio fx-9750 G II, Casio fx-9750 G II (SH4), Casio fx-9860G, Casio fx-9860 G SD, Casio fx-9860G Slim, Casio fx-9860 GII SD, Casio fx-9860 GII SD Power Graphic 2, Casio Classpad 330 plus, Casio fx-CG 20, Casio Classpad fx-cp400, Casio fx-CG 50

Re: No FPU in fx-9860G II?

Postby SimonLothar » Sun Feb 17, 2019 1:36 pm

Perhaps the following list comes in handy in some situations:
SH7305 Pin Function Controller port assignments: Show
PTA0 (1) : Port A0 / FSI_LRCK / MSIOF0_TSYNC in
PTA0 (2) : Port A0 / FSI_LRCK / CLK1 / MSIOF0_TSYNC out
PTA1 (1) : Port A1 / FSI_BCK / MSIOF0_TSCK in
PTA1 (2) : Port A1 / FSI_BCK / CLK2 / MSIOF0_TSCK out
PTA2 (1) : Port A2 in
PTA2 (2) : Port A2 / FSI_OSD / TXD / MSIOF0_TXD out
PTA3 (1) : Port A3 / FSI_ISD / RXD / MSIOF0_RXD in
PTA3 (2) : Port A3 out
PTA4 (1) : Port A4 / FSI_MCK / MSIOF0_MCK in
PTA4 (2) : Port A4 / FSI_MCK / CLK2 / MSIOF0_MCK out
PTB0 (1) : Port B0 in
PTB0 (2) : Port B0 / NA_CDE / ESD_CLKA / EMMC_CLKA out
PTB1 (1) : Port B1 / ESD_CMDA / EMMC_CMDA in
PTB1 (2) : Port B1 / NA_SC / ESD_CMDA / EMMC_CMDA out
PTB2 (1) : Port B2 / ESD_DATA0A / EMMC_DATA0A in
PTB2 (2) : Port B2 / NA_OE / ESD_DATA0A / EMMC_DATA0A out
PTB3 (1) : Port B3 / NA_RYBY / ESD_DATA1A / EMMC_DATA1A in
PTB3 (2) : Port B3 / ESD_DATA1A / EMMC_DATA1A out
PTB4 (1) : Port B4 / ESD_DATA2A / EMMC_DATA2A in
PTB4 (2) : Port B4 / NA_WE / ESD_DATA2A / EMMC_DATA2A out
PTB5 (1) : Port B5 / ESD_DATA3A / EMMC_DATA3A in
PTB5 (2) : Port B5 / NA_CE1 / ESD_DATA3A / EMMC_DATA3A out
PTC0 (1) : Port C0 / EMMC_DATA4A in
PTC0 (2) : Port C0 / NA_CE2 / CS2B / EMMC_DATA4A out
PTC1 (1) : Port C1 / EMMC_DATA5A in
PTC1 (2) : Port C1 / NA_CE3 / CS3B / EMMC_DATA5A out
PTC2 (1) : Port C2 / NA_IO7 / EMMC_DATA6A in
PTC2 (2) : Port C2 / NA_IO7 / CS4B / EMMC_DATA6A in
PTC3 (1) : Port C3 / NA_IO6 / EMMC_DATA7A in
PTC3 (2) : Port C3 / NA_IO6 / EMMC_DATA7A out
PTC4 (1) : Port C4 in
PTC4 (2) : Port C4 / NA_WP out
PTC5 (1) : Port C5 in
PTC5 (2) : Port C5 / NA_ON out
PTD0 (1) : Port D0 / NA_IO5 in
PTD0 (2) : Port D0 / NA_IO5 / ESD_CLKB / EMMC_CLKB out
PTD1 (1) : Port D1 / NA_IO4 in
PTD1 (2) : Port D1 / NA_IO4 / ESD_CMDB / EMMC_CMDB out
PTD2 (1) : Port D2 / NA_IO3 / ESD_DATA0B / EMMC_DATA0B in
PTD2 (2) : Port D2 / NA_IO3 / ESD_DATA0B / EMMC_DATA0B out
PTD3 (1) : Port D3 / NA_IO2 / ESD_DATA1B / EMMC_DATA1B in
PTD3 (2) : Port D3 / NA_IO2 / ESD_DATA1B / EMMC_DATA1B out
PTD4 (1) : Port D4 / NA_IO1 / ESD_DATA2B / EMMC_DATA2B in
PTD4 (2) : Port D4 / NA_IO1 / ESD_DATA2B / EMMC_DATA2B out
PTD5 (1) : Port D5 / NA_IO0 / ESD_DATA3B / EMMC_DATA3B in
PTD5 (2) : Port D5 / NA_IO0 / ESD_DATA3B / EMMC_DATA3B out
PTE0 (1) : Port E0 in
PTE0 (2) : Port E0 / A0 out
PTE1 (1) : Port E1 in
PTE1 (2) : Port E1 / A22 out
PTE2 (1) : Port E2 in
PTE2 (2) : Port E2 / A23 out
PTE3 (1) : Port E3 in
PTE3 (2) : Port E3 / A24 out
PTE4 (1) : Port E4 in
PTE4 (2) : Port E4 / A25 out
PTF0 (1) : Port F0 in
PTF0 (2) : Port F0 / BS / CLK3 / C_DA out
PTF1 (1) : Port F1 in
PTF1 (2) : Port F1 / RD out
PTF2 (1) : Port F2 in
PTF2 (2) : Port F2 / WE0 / DQMLL out
PTF3 (1) : Port F3 in
PTF3 (2) : Port F3 / WE1 / DQMLU out
PTF4 (1) : Port F4 in
PTF4 (2) : Port F4 / RASL out
PTF5 (1) : Port F5 in
PTF5 (2) : Port F5 / CASL out
PTF6 (1) : Port F6 in
PTF6 (2) : Port F6 / CKE out
PTF7 (1) : Port F7 / WAIT in
PTF7 (2) : Port F7 / CLK1 out
PTG0 (1) : Port G0 in
PTG0 (2) : Port G0 / AUDATA0 / TPO0 out
PTG1 (1) : Port G1 in
PTG1 (2) : Port G1 / AUDATA1 / TPO1 out
PTG2 (1) : Port G2 in
PTG2 (2) : Port G2 / AUDATA2 / TPO2 out
PTG3 (1) : Port G3 in
PTG3 (2) : Port G3 / AUDATA3 / TPO3 out
PTG4 (1) : Port G4 in
PTG4 (2) : Port G4 / AUDSYNC / TPO4 out
PTG5 (1) : Port G5 in
PTG5 (2) : Port G5 / AUDCK / TPO5 out
PTG6 (1) : Port G6 in
PTG6 (2) : Port G6 / TPO6 / CLK1 out
PTG7 (1) : Port G7 in
PTG7 (2) : Port G7 / TPO7 out
PTH0 (1) : Port H0 in
PTH0 (2) : Port H0 / CS6A / NA_CE4 / C_DA out
PTH1 (1) : Port H1 in
PTH1 (2) : Port H1 / CS6B / NA_CE5 out
PTH2 (1) : Port H2 in
PTH2 (2) : Port H2 / DDCS1 / CS50 out
PTH3 (1) : Port H3 in
PTH3 (2) : Port H3 / DDCS2 / CS51 out
PTH4 (1) : Port H4 in
PTH4 (2) : Port H4 / DACK0 / MSIOF11_SS1 / TXD out
PTH5 (1) : Port H5 / RXD in
PTH5 (2) : Port H5 / DACKL0 / MSIOF11_SS2 out
PTH6 (1) : Port H6 / DREQ0 in
PTH6 (2) : Port H6 / STATUS2 out
PTJ0 (1) : Port J0 / MSIOF1_TSCK / SCK in
PTJ0 (2) : Port J0 / RTS / MSIOF1_TSCK / SCK out
PTJ1 (1) : Port J1 / CTS / MSIOF_TSYNC in
PTJ1 (2) : Port J1 / MSIOF_TSYNC / STATUS0 in
PTJ2 (1) : Port J2 in
PTJ2 (2) : Port J2 / TXD / MSIOF1_TXD / STATUS1 out
PTJ3 (1) : Port J3 / RXD / MSIOF1_RXD in
PTJ3 (2) : Port J3 out
PTJ4 (1) : Port J4 / SCL in
PTJ4 (2) : SCL out
PTJ5 (1) : Port J5 / SDA in
PTJ5 (2) : SDA out
PTJ6 (1) : Port J6 in
PTJ6 (2) : Port J6 / POCNTB out
PTK0 (1) : Port K0 / SD_DATA0 in
PTK0 (2) : Port K0 / SD_DATA0 out
PTK1 (1) : Port K1 / SD_DATA1 in
PTK1 (2) : Port K1 / SD_DATA1 out
PTK2 (1) : Port K2 / SD_DATA2 in
PTK2 (2) : Port K2 / SD_DATA2 out
PTK3 (1) : Port K3 / SD_DATA3 in
PTK3 (2) : Port K3 / SD_DATA3 out
PTK4 (1) : Port K4 / SD_DET / PINT0 in
PTK4 (2) : Port K4 out
PTK5 (1) : Port K5 / SD_WP in
PTK5 (2) : Port K5 out
PTK6 (1) : Port K6 / SD_CMD in
PTK6 (2) : Port K6 / SD_CMD out
PTK7 (1) : Port K7 in
PTK7 (2) : Port K7 / SD_CLK out
PTL0 (1) : Port L0 / IRQ0 / PINT4 in
PTL0 (2) : Port L0 out
PTL1 (1) : Port L1 / IRQ1 / PINT5 in
PTL1 (2) : Port L1 out
PTL2 (1) : Port L2 / IRQ2 / PINT6 in
PTL2 (2) : Port L2 out
PTL3 (1) : Port L3 / IRQ3 / PINT7 in
PTL3 (2) : Port L3 out
PTM0 (1) : Port M0 / PINT12 in
PTM0 (2) : Port M0 / KO0 out
PTM1 (1) : Port M1 / PINT13 in
PTM1 (2) : Port M1 / KO1 out
PTM2 (1) : Port M2 / PINT14 in
PTM2 (2) : Port M2 / KO2 out
PTM3 (1) : Port M3 / PINT15 in
PTM3 (2) : Port M3 / KO3 out
PTM4 (1) : Port M4 / PINT16 in
PTM4 (2) : Port M4 / KO4 / TPO0 out
PTM5 (1) : Port M5 / PINT17 in
PTM5 (2) : Port M5 / KO5 / TPO1 out
PTN0 (1) : Port N0 / PINT18 in
PTN0 (2) : Port N0 / KO6 / TPO2 out
PTN1 (1) : Port N1 / PINT19 in
PTN1 (2) : Port N1 / KO7 / TPO3 out
PTN2 (1) : Port N2 / PINT20 in
PTN2 (2) : Port N2 / KO8 / TPO4 out
PTN3 (1) : Port N3 / PINT21 in
PTN3 (2) : Port N3 / KO9 / TPO5 out
PTN4 (1) : Port N4 / PINT22 in
PTN4 (2) : Port N4 / KO10 / TPO6 out
PTN5 (1) : Port N5 / PINT23 in
PTN5 (2) : Port N5 / KO11 / TPO7 out
PTP0 (1) : Port P0 / KI0 / PINT24 in
PTP0 (2) : Port P0 out
PTP1 (1) : Port P1 / KI1 / PINT25 in
PTP1 (2) : Port P1 out
PTP2 (1) : Port P2 / KI2 / PINT26 in
PTP2 (2) : Port P2 out
PTP3 (1) : Port P3 / KI3 / PINT27 in
PTP3 (2) : Port P3 out
PTP4 (1) : Port P4 / KI4 / PINT28 in
PTP4 (2) : Port P4 out
PTP5 (1) : Port P5 / KI5 / PINT29 in
PTP5 (2) : Port P5 out
PTP6 (1) : Port P6 / KI6 / PINT30 in
PTP6 (2) : Port P6 out
PTP7 (1) : Port P7 / KI7 / PINT31 in
PTP7 (2) : Port P7 out
PTQ0 (1) : Port Q0 / TDI in
PTQ1 (1) : Port Q1 / TCK in
PTQ2 (1) : Port Q2 / TMS in
PTQ3 (1) : Port Q3 / TRST in
PTQ4 (2) : Port Q4 / TDO out
PTQ5 (1) : Port Q5 / ASEBRK in
PTQ5 (2) : Port Q5 / ASEBRK out
PTR0 (1) : Port R0 in
PTR0 (2) : Port R0 / CS52 / C_DA out
PTR1 (1) : Port R1 in
PTR1 (2) : Port R1 / CS53 / C_DA out
PTR2 (1) : Port R2 in
PTR2 (2) : Port R2 / CS2 / CS2A / C_DA out
PTR3 (1) : Port R3 in
PTR3 (2) : Port R3 / CS3 / CS3A / C_DA out
PTR4 (1) : Port R4 in
PTR4 (2) : Port R4 / CS4 / CS4A / C_DA out
PTR5 (1) : Port R5 / PINT2 in
PTR5 (2) : Port R5 / CS5A / MSIOF1_SS1 out
PTR6 (1) : Port R6 / PINT3 in
PTR6 (2) : Port R6 / CS5B / MSIOF1_SS2 out
PTS0 (1) : Port S0 / PINT8 in
PTS0 (2) : Port S0 / SHOC_MREQ out
PTS1 (1) : Port S1 / SHOC_MIGNT in
PTS1 (2) : Port S1 out
PTS2 (1) : Port S2 / SHOC_MTGNT in
PTS2 (2) : Port S2 out
PTS3 (1) : Port S3 / PINT9 in
PTS3 (2) : Port S3 / SHOC_MEOP out
PTS4 (1) : Port S4 / PINT10 in
PTS4 (2) : Port S4 / SHOC_MBE out
PTS5 (1) : Port S5 / SHOC_SEN / PINT1 in
PTS5 (2) : Port S5 out
PTS6 (1) : Port S6 in
PTS6 (2) : Port S6 / SHOC_MEN out
PTS7 (1) : Port S7 in
PTS7 (2) : Port S7 / SHOC_MCLKO out
PTT0 (1) : Port T0 in
PTT0 (2) : Port T0 / SHOC_MDATA0 / TPO0 out
PTT1 (1) : Port T1 in
PTT1 (2) : Port T1 / SHOC_MDATA1 / TPO1 out
PTT2 (1) : Port T2 in
PTT2 (2) : Port T2 / SHOC_MDATA2 / TPO2 out
PTT3 (1) : Port T3 in
PTT3 (2) : Port T3 / SHOC_MDATA3 / TPO3 out
PTT4 (1) : Port T4 in
PTT4 (2) : Port T4 / SHOC_MDATA4 / TPO4 out
PTT5 (1) : Port T5 in
PTT5 (2) : Port T5 / SHOC_MDATA5 / TPO5 out
PTT6 (1) : Port T6 in
PTT6 (2) : Port T6 / SHOC_MDATA6 / TPO6 out
PTT7 (1) : Port T7 in
PTT7 (2) : Port T7 / SHOC_MDATA7 / TPO7 out
PTU0 (1) : Port U0 / SHOC_SREQ in
PTU0 (2) : Port U0 out
PTU1 (1) : Port U1 / PINT11 in
PTU1 (2) : Port U1 / SHOC_SIGNT out
PTU2 (1) : Port U2 in
PTU2 (2) : Port U2 / SHOC_STGNT out
PTU3 (1) : Port U3 / SHOC_SEOP in
PTU3 (2) : Port U3 out
PTU4 (1) : Port U4 / SHOC_SBE in
PTU4 (2) : Port U4 out
PTV0 (1) : Port V0 / SHOC_SDATA0 in
PTV0 (2) : Port V0 out
PTV1 (1) : Port V1 / SHOC_SDATA1 in
PTV1 (2) : Port V1 out
PTV2 (1) : Port V2 / SHOC_SDATA2 in
PTV2 (2) : Port V2 out
PTV3 (1) : Port V3 / SHOC_SDATA3 in
PTV3 (2) : Port V3 out
PTV4 (1) : Port V4 / SHOC_SDATA4 in
PTV4 (2) : Port V4 out
PTV5 (1) : Port V5 / SHOC_SDATA5 in
PTV5 (2) : Port V5 out
PTV6 (1) : Port V6 / SHOC_SDATA6 in
PTV6 (2) : Port V6 out
PTV7 (1) : Port V7 / SHOC_SDATA7 in
PTV7 (2) : Port V7 out
I'll be back!

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Calculators: Casio Cfx Series, Casio fx-9860G, Casio fx-9860 GII, Casio fx-9860 GII SD Power Graphic 2, Casio fx-CG 10, Casio fx-CG 20, Casio fx-CG 50

Re: No FPU in fx-9860G II?

Postby sentaro21 » Thu Feb 21, 2019 7:40 am

Your complete list of registers is very useful.
My add-ins can not exist without your list or information.
Thanks very much! :D

By the way, this is one question.
About SSCGCR (Spread spectrum control),
This seems not to be in SH7724, but does any other CPU have SSCGCR?

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Calculators: Casio fx-7400GII, Casio fx-7400GII (SH4), Casio fx-9750 G II, Casio fx-9750 G II (SH4), Casio fx-9860G, Casio fx-9860 G SD, Casio fx-9860G Slim, Casio fx-9860 GII SD, Casio fx-9860 GII SD Power Graphic 2, Casio Classpad 330 plus, Casio fx-CG 20, Casio Classpad fx-cp400, Casio fx-CG 50

Re: No FPU in fx-9860G II?

Postby SimonLothar » Sat Feb 23, 2019 2:05 pm

sentaro21 wrote:By the way, this is one question.
About SSCGCR (Spread spectrum control),
This seems not to be in SH7724, but does any other CPU have SSCGCR?

There is a register OSCWTCR with the same address on the SH7730, but I do not know, if it is related to SH7305 SSCGCR.
Above that I could not find any clues in the MPU-manuals I have at hand.
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Posts: 30
Joined: Mon Oct 27, 2014 1:46 pm
Location: Japan
Calculators: Casio Cfx Series, Casio fx-9860G, Casio fx-9860 GII, Casio fx-9860 GII SD Power Graphic 2, Casio fx-CG 10, Casio fx-CG 20, Casio fx-CG 50

Re: No FPU in fx-9860G II?

Postby sentaro21 » Sun Feb 24, 2019 5:46 am

Thanks!
I confirmed that it is a function different from spread spectrum in the manual of SH7730.
I think that it is so wonderful that you found the SSCGCR of SH7305. :thumbup:
Thanks very much again! :D

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