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Link port anatomy on fx-860gii hardware

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Link port anatomy on fx-860gii hardware

Postby Jsec42 » Mon Oct 05, 2015 11:36 pm

I have been looking over existing documentation/code concerning the link port on the Casio 9860g series link ports, and spotted some peculiarities. Needless to say I have a few questions about it:

1. Is it possible to set both pins to transmit/receive independently of each other?
2. If this is not possible, is it at least possible to switch whether the tip/ring is used to transmit/receive?

The reason why I ask this is because I am working on a couple of projects that would require said functionality to function correctly. I have already determined that voltages are at least legible by the hardware I'm working with, however its linking protocol requires some additional leeway for reception. Thanks in advance! ;)

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Re: Link port anatomy on fx-860gii hardware

Postby SimonLothar » Fri Oct 09, 2015 5:24 pm

I once uploaded a program here. I contains the source to access the serial pins directly (using the pin function controller). Though, the serial output cannot be used as input. If I remember well, the serial input can be used as output, too. In this mode you'd have to provide for the proper signal widths and timing yourself. If you use the pins with the serial communication interface the pins cannot be switched, except with a straight through cable.
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Re: Link port anatomy on fx-860gii hardware

Postby Jsec42 » Sat Oct 10, 2015 12:40 am

I see...Actually I have been using your program's source as a reference while I did some of my own investigation. I am still trying to find out how to output to the serial receive pin, and receive through the transmit pin(as I am pretty sure DBus requires the initial transfer to always occur on the "tip" line, the standard transmit-receive model would work for transmission, but I would need to reverse the pins in order to receive data.).

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Re: Link port anatomy on fx-860gii hardware

Postby Jsec42 » Sat Oct 10, 2015 12:42 am

Though the ability to transmit on both pins may lead to some pretty killer sound apps ;)

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Re: Link port anatomy on fx-860gii hardware

Postby Jsec42 » Sat Oct 10, 2015 12:46 am

And as a note, DBus doesn't require the two units to run at the same clock speed - The transmission/receive speed is limited by host-client latency. So I guess what I'm saying is that I don't quite understand the SH3/4a Control/Data port architecture, nor am I aware of which port letters map to which hardware device(Though I did notice some interesting similarities between the TI-83+ lcd controller and the one the Casio 9860g series uses)

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Re: Link port anatomy on fx-860gii hardware

Postby -florian66- » Wed Oct 14, 2015 6:53 pm

Hi !
i work to make music on Casio g75
Can you explain me how to use the serial input port as output to make stereo sounds ? I'm on Sh4 ;)

At present, I try to find the serial output buffer to put data in and I don't find :yawn: However, I disassembled the OS and I have found addresses but I don't know if they are right ...
i've got several addresses like 0x88 00 B9 1C or 0x88 00 B5 14 ...

Can you help me ?
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Re: Link port anatomy on fx-860gii hardware

Postby SimonLothar » Fri Oct 16, 2015 4:17 pm

You have to use the pins 2 and 3 of port J (hint: the pin function controller of the SH7305 is completely incompatible compared to the SH7724).
Program them to output (after initializing the hardware according to the source I mentioned some posts above).

#define SH7305_PJCR 0xA4050110
#define SH7305_PJDR 0xA4050130

// set port J bit 2 to output mode
*(unsigned short*)SH7305_PJCR = ( *(unsigned short*)SH7305_PJCR & ~0x0030 ) | 0x0010;
// set port J bit 3 to output mode
*(unsigned short*)SH7305_PJCR = ( *(unsigned short*)SH7305_PJCR & ~0x00C0 ) | 0x0040;


// set/clear port J bit 2
if ( state ) *(unsigned char*)SH7305_PJDR |= 0x04;
else *(unsigned char*)SH7305_PJDR &= ~0x04;
// set/clear port J bit 3 (this pin operates inversely)
if ( !state ) *(unsigned char*)SH7305_PJDR |= 0x08;
else *(unsigned char*)SH7305_PJDR &= ~0x08;

I just tried it and the outputs nicely switched between 0 and 3 V.
But I did not check the dynamics. Possibly the receive pin tends to signal damping at higher frequencies.

This works with the SH7305 only. With SH7337/SH7355 the RXD- and TXD-pins internally share the same port bit.
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Re: Link port anatomy on fx-860gii hardware

Postby Jsec42 » Fri Oct 16, 2015 5:14 pm

I see now how this works, thanks! :D I will tinker around with this code and see where it can take me. Just as a question, since I cannot test on the platform, is it possible for the SH3 calculators to switch what writing/reading the bit does to the serial output/input pins(ie would it be possible to cause the receive pin to transmit and the transmit pin to receive?), Because I don't want to make an app that only Gii-2 models can use.

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Re: Link port anatomy on fx-860gii hardware

Postby -florian66- » Fri Oct 16, 2015 5:35 pm

Oh thanks a lot :D but how do you know that ? Do you have a doc about that ?

i'm only on SH7305 so it's good :)

I have to find good frequencies betwenn the two ports ;)

i had a look on Dserial and the code source is not complete.
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Re: Link port anatomy on fx-860gii hardware

Postby SimonLothar » Fri Oct 16, 2015 6:18 pm

Jsec42 wrote:Just as a question, since I cannot test on the platform, is it possible for the SH3 calculators to switch what writing/reading the bit does to the serial output/input pins(ie would it be possible to cause the receive pin to transmit and the transmit pin to receive?)...
If you look at the 7705-MPU-manual (V 2.00) page 478, the port SC bit 0 is used for RXD and TXD in common. Seems to be fixed. I fear there is no way around.
Jsec42 wrote:...Because I don't want to make an app that only Gii-2 models can use.
On SH7337/SH7355-based calculators you will only produce mono-output. But most of your program should work properly on any fx9860.
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